1. Field of the Invention
The present invention relates to a data processing system having a cache memory and an address converter for converting a virtual address into a real address in a main storage apparatus and, more particularly, to a data processing system capable of executing a microinstruction subsequent to a write microinstruction without a wait time, even when a cache hit does not occur during execution of the write microinstruction.
2. Related Art of the Invention
Conventional data processing systems, whether comprising a main storage apparatus having a relatively small capacity as a storage apparatus having a relatively large capacity, both employ a virtual storage scheme. In this scheme, a virtual address is converted into a real address by an address conversion section positioned in the main storage apparatus. Generally, a processor in such a data processing system incorporates a cache memory section of a store-through scheme.
In such a data processing system, when a read microinstruction is executed and a miss-hit occurs in the cache memory, a virtual address is converted into a real address, and data is read out from the real address in the main storage apparatus into the processor. If a real address is not present in the main storage apparatus, a missing page signal is supplied to the processor. After the execution of the read microinstruction, therefore, the processor must withhold execution of the next microinstruction until the data or the missing page signal is input.
When a write microinstruction is to be executed, the processor can sometimes execute the next microinstruction without waiting for a response from the main storage apparatus. If, however, a real address corresponding to a virtual address is not present in the main storage apparatus, data cannot be written in the main storage apparatus. In this case, write processing is temporarily stopped, and an external storage apparatus must be accessed. When a microinstruction is to be executed immediately after the execution of the write microinstruction, some microinstructions may have been executed by the time a missing page signal is supplied to the processor. In this case, the processor must be returned to its original state, and hence requires complicated hardware.
For this reason, the conventional data processing system employs a scheme wherein after a write microinstruction is executed, execution of a subsequent microinstruction is delayed until a write end response or a missing page signal is supplied from the main storage apparatus. In such a scheme, however, since a wait occurs for each execution of a write microinstruction, the processing speed is decreased.